The present invention relates to a semiconductor memory device suitable for an electrically erasable and electrically programmable read-only memory.
Writing and erasing of data after manufacture is possible with an erasable and electrically programmable read-only memory (EP-ROM). The EP-ROMs are roughly classified into the ultraviolet ray erasable type and into the electrically erasable type. A high packaging density may be accomplished with an EP-ROM of the ultraviolet ray erasable type, since one transistor may comprise one memory cell. The ultraviolet ray erasable type EP-ROMs of 32 kbit and 64 kbit sizes have been developed so far. However, the EP-ROMs of the ultraviolet ray erasable type are defective in that manufacturing cost becomes high since a package is required which transmits the ultraviolet rays. On the other hand, a satisfactory packaging density may not be accomplished with the electrically erasable and programmable read-only memory (E.sup.2 P-ROM) since at least two transistors constitute one memory cell. E.sup.2 P-ROMs of 16 kbit have so far been developed. However, the E.sup.2 P-ROMs of the electrically erasable type are advantageous in that manufacturing costs may be reduced by using a less expensive plastic material for the package.
FIG. 1 is a circuit diagram of a memory cell of a conventional E.sup.2 P-ROM disclosed in "A 16 kb Electrically Erasable Nonvolatile Memory", ISSCC Digest of Technical Papers, 1980, Feb. pp 152 to 153 and 271 by W. S. Johnson et al. This memory cell comprises two transistors Q1 and Q2. The transistor Q1 comprises a select MOS transistor and the transistor Q2 comprises a double gate type MOS transistor having a control gate 50 and a floating gate 52. One doped region of the transistor Q1 is connected to a digit line 54, and the other doped region thereof is connected to one doped region of the transistor Q2. The gate of the transistor Q1 is connected to a select line 56. The other doped region of the transistor Q2 is grounded, and the control gate thereof is connected to a data program line 58.
The conventional E.sup.2 P-ROMs of the construction as described above have the following drawbacks:
(a1) As may be apparent from FIG. 1, one memory cell comprises two transistors. Therefore, the number of elements becomes twice that of the EP-ROMs of the ultraviolet ray erasable type, resulting in half the packaging density. The EP-ROMs of the electrically erasable type are inferior in the packaging density to those of the ultraviolet ray erasable type.
(a2) Voltages of both polarities of positive and negative are required for writing and erasing of data. Therefore, power sources of both polarities of positive and negative are required for mounting the E.sup.2 P-ROMs of this type on a printed circuit board and for electrically writing and erasing data therein.
(a3) Extra circuits are required to simultaneously erase data in units of words or all the bits, resulting in a low packaging density.
(a4) It is difficult to erase data of all the bits within a short period of time.
(a5) It is impossible to erase data with a unipolar power source of 5 V, for example.
An E.sup.2 P-ROM which eliminates the above drawbacks is disclosed in "Triple Level Poly-silicon E.sup.2 P-ROM with Single Transistor Per Bit", J. Kupec, W. M. Gosney, V. Mckenny, and V. Kowshik, IEDM, Dec. 1980, pp 602 to 606. In the paper described above, a method for preventing excessive erasure of data from the floating gate is disclosed. The present invention provides a semiconductor memory device which prevents excessive erasure of data from the floating gate by a different method from the method described in the paper.